Lehigh University - CSE: Garcia

Philip Garcia

"A Reconfigurable Hardware Interface for Modern Computing Systems"

Thursday, November 15, Noon

Packard Lab Room 360

Computer architects have recently been struggling to efficiently utilize the increasing number of transistors available on a single microprocessor A combination of limited instruction level parallelism and constrained power requirements have made it no longer economical to push single-threaded performance. While many vendors are currently exploring many-core processors, it is unknown how efficiently this trend can continue.

It is our belief that reconfigurable processors, when combined with traditional processor cores can help increase application performance even more. Reconfigurable computing utilizes hardware accelerators to greatly improve the performance of an application. Such techniques have been used extensively in building custom hardware on FPGAs, however current implementations limit the reconfigurability of the hardware, and do not provide an efficient method for the reconfigurable hardware to communicate with general-purpose processors.

In this talk, I will discuss the challenges that are involved in coupling reconfigurable hardware with general-purpose processors and their memory subsystem. I will examine techniques that we have developed to alow the reconfigurable hardware to efficiently access virtual memory, and communicate with the system's processor(s). Additionally I will describe a simulator that we have developed to examine the performance of our reconfigurable hardware interface.

Phil Garcia obtained his undergraduate degree in Computer Engineering at Lehigh University in 2004. After obtaining his undergraduate degree, he continued his education at Lehigh under Dr. Henry Korth studying architectural aware database systems. In 2005, he obtained his MS, and started his PhD at the University of Wisconsin-Madison where he works under Dr. Katherine Compton. He is currently researching new architectures for reconfigurable computing.

		Philip Garcia "A Reconfigurable Hardware Interface for Modern Computing Systems" Thursday, November 15, Noon Packard Lab Room 360 Computer architects have recently been struggling to efficiently utilize the increasing number of transistors available on a single microprocessor A combination of limited instruction level parallelism and constrained power requirements have made it no longer economical to push single-threaded performance. While many vendors are currently exploring many-core processors, it is unknown how efficiently this trend can continue. It is our belief that reconfigurable processors, when combined with traditional processor cores can help increase application performance even more. Reconfigurable computing utilizes hardware accelerators to greatly improve the performance of an application. Such techniques have been used extensively in building custom hardware on FPGAs, however current implementations limit the reconfigurability of the hardware, and do not provide an efficient method for the reconfigurable hardware to communicate with general-purpose processors. In this talk, I will discuss the challenges that are involved in coupling reconfigurable hardware with general-purpose processors and their memory subsystem. I will examine techniques that we have developed to alow the reconfigurable hardware to efficiently access virtual memory, and communicate with the system's processor(s). Additionally I will describe a simulator that we have developed to examine the performance of our reconfigurable hardware interface. Phil Garcia obtained his undergraduate degree in Computer Engineering at Lehigh University in 2004. After obtaining his undergraduate degree, he continued his education at Lehigh under Dr. Henry Korth studying architectural aware database systems. In 2005, he obtained his MS, and started his PhD at the University of Wisconsin-Madison where he works under Dr. Katherine Compton. He is currently researching new architectures for reconfigurable computing.