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Prof. Richard Hughey "Melding Algorithms and Architectures with the UCSC Kestrel Parallel Processor" Monday, January 29, 3:00 PM Packard Lab -- 466
Architects and industry have been searching for the next durable computational model, the next step beyond the standard CPU. Graphics co-processors, though ubiquitous and powerful, can only be effectively used on a limited range of stream-based applications. The UCSC Kestrel parallel processor is part of an evolution from application-specific to specialized to application-unspecific parallel processing. Kestrel combines an ALU, multiplier, and local memory, with Systolic Shared Registers for seamless merging of communication and computation, and an innovative condition stack for rapid conditionals. The result has been a readily programmable and efficient co-processor for a wide range of applications, including biological sequence analysis, image processing, and irregular problems. Experience with Kestrel indicates that programmable systolic processing, and its natural combination with the Single Instruction-Multiple Data (SIMD) parallel architecture, is one of the most powerful, flexible, and power-efficient computational models available. This talk will include an overview of approaches to biological sequence analysis, an analysis of the Kestrel architecture, and a discussion of algorithms that motivated Kestrel and were motivated by Kestrel.
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