Wednesday, February 25, 4:00 PM

Packard Lab room 466

Reception prior to talk in Packard Lobby

Abstract: Most abstractions in computing hide timing properties of software. As a result, computer architects, and language and compiler designers use clever techniques to improve the average-case performance. This, however, is at the expense of predictable and repeatable timing. We find these techniques to be problematic for real-time embedded computing because they result in unpredictable and non-repeatable behavior, and brittle systems.

Our approach treats time as a first-class property of embedded computing. While this requires redesigning multiple abstraction layers in computing, our current focus is on the hardware design of a real-time embedded processor that we term the precision timed (PRET) architecture. PRET's objective is to judiciously select architectural optimization techniques to deliver performance enhancements, but without sacrificing timing predictability and repeatability. In addition, we extend the instruction-set architecture with instructions to control execution time.  We believe that timing predictability and repeatability are not at odds with performance.

Bio:  Hiren is a post doctoral scholar at U.C. Berkeley. He is leading a research project on precision timed architectures. Hiren's research interests include system-level design methodologies, models of computation, real-time systems, embedded processor architectures, simulation and verification. He has published several articles in journal and conference proceedings, book chapters and co-authored two books.