Lehigh University - CSE:Spear Fall 09

Dr. Michael F. Spear

"Square Pegs, Round Holes: Computer Science in the Multi-core Era"

Wednesday, October 14, 4:00 PM

Packard Lab room 466

Reception prior to talk in Packard Lobby

Abstract: Since 2004, microprocessor vendors have embraced multi-core processors as the primary means of increasing performance. This decision was not, unfortunately, driven by demand. Though multi-core processors are capable of much higher throughput than their single-core ancestors, that potential is rarely enjoyed by existing software. Today’s programs are rarely written in a way that is amenable to parallel execution, and even among those programs written to exploit parallelism, few succeed in achieving sufficient speedup on multi-core machines.

In this presentation, I will discuss the background of how the computing industry came to find itself in this awkward situation. I will then introduce a number of innovations in hardware, languages, and compilers, that aim to improve the performance and parallelism of existing and emerging software. Taking a cue from the techniques that drove microprocessor performance during the 1990s, these innovations largely focus on the role that explicit and implicit speculation can play in decreasing latency and increasing throughput. Lastly, I will propose a strategy for anticipating and preparing to handle the next major shift in microprocessor design, so that computer scientists can prevent history from repeating itself.

Bio: Michael Spear is an assistant professor of Computer Science and Engineering at Lehigh University. He received his PhD in Computer Science at the University of Rochester in 2009, his MS in Computer Science from the University of Rochester in 2005, an MBA from the University of Alaska, Anchorage, in 2003, and his BS degree in Computer Science from the United States Military Academy in 1999. His research interests are in the area of parallel systems, with an emphasis on the design and implementation of algorithms, run-time systems, and hardware features to increase the efficiency of shared memory synchronization. He is currently investigating a wide range of issues related to the implementation of efficient transactional memory, including algorithms, language-level semantics, operating system interaction, compiler optimizations, and cache coherence protocols.

		Dr. Michael F. Spear "Square Pegs, Round Holes: Computer Science in the Multi-core Era" Wednesday, October 14, 4:00 PM Packard Lab room 466 Reception prior to talk in Packard Lobby Abstract: Since 2004, microprocessor vendors have embraced multi-core processors as the primary means of increasing performance. This decision was not, unfortunately, driven by demand. Though multi-core processors are capable of much higher throughput than their single-core ancestors, that potential is rarely enjoyed by existing software. Today’s programs are rarely written in a way that is amenable to parallel execution, and even among those programs written to exploit parallelism, few succeed in achieving sufficient speedup on multi-core machines. In this presentation, I will discuss the background of how the computing industry came to find itself in this awkward situation. I will then introduce a number of innovations in hardware, languages, and compilers, that aim to improve the performance and parallelism of existing and emerging software. Taking a cue from the techniques that drove microprocessor performance during the 1990s, these innovations largely focus on the role that explicit and implicit speculation can play in decreasing latency and increasing throughput. Lastly, I will propose a strategy for anticipating and preparing to handle the next major shift in microprocessor design, so that computer scientists can prevent history from repeating itself. Bio: Michael Spear is an assistant professor of Computer Science and Engineering at Lehigh University. He received his PhD in Computer Science at the University of Rochester in 2009, his MS in Computer Science from the University of Rochester in 2005, an MBA from the University of Alaska, Anchorage, in 2003, and his BS degree in Computer Science from the United States Military Academy in 1999. His research interests are in the area of parallel systems, with an emphasis on the design and implementation of algorithms, run-time systems, and hardware features to increase the efficiency of shared memory synchronization. He is currently investigating a wide range of issues related to the implementation of efficient transactional memory, including algorithms, language-level semantics, operating system interaction, compiler optimizations, and cache coherence protocols.